The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A FET includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions. The FETs are generally “N” or “P” type FETs, (“nFET” or “pFET”) where the source and drain for nFETs are implanted with “N” type conductivity-determining ions, and the source and drain for pFETs are implanted with “P” type conductivity determining ions.
The gate electrode may be a replacement metallic gate, where a temporary, sacrificial gate, which is called a “dummy” gate, is initially formed while other components of the FET are produced. A dielectric column is formed overlying the source and drain, and the dummy gate is removed from between adjacent dielectric columns. The dielectric column may include a dielectric barrier and a dummy core. The replacement metallic gate is then formed, and the dummy cores are removed and replaced with contacts extending upward from the source and drain. The dielectric barrier, which is commonly known as a spacer, is between and physically separates the replacement metallic gate and the contact. Therefore, the dielectric barrier insulates the contact from the replacement metallic gate, but the dielectric barrier ends at the dielectric column top surface. In some cases, a short may develop where the replacement metallic gate becomes electrically connected with the contacts at or near the dielectric column top surface. The replacement metallic gate may be recessed to a lower level to increase the amount of dielectric barrier between the replacement metallic gate and the contact, and thereby reduce the chance of a short.
The integrated circuit may include different types of replacement metallic gates, where some are formed in a short region with a short region width and some are formed in a long region with a longer width. Somewhat different processes are conventionally used to recess the replacement metallic gate in the short regions as compared to recessing the replacement metallic gate in the long regions, and lithographic processes may be used for the different processes. Lithographic processes are one of the more expensive processes in the manufacture of integrated circuits.
Accordingly, it is desirable to provide integrated circuits and methods of manufacturing integrated circuits with replacement metallic gates having different widths, where the production process uses a reduced number of lithographic processes. Other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.